Comment on Intel CPU Temperature Monitoring Driver For Linux Now Unmaintained After Layoffs

• Eknz@lemmy.eknz.org ⁨2⁩ ⁨months⁩ ago

  It doesn’t really make much of a difference on modern CPUs as instructions are broken down into RISC-like operands even on CISC CPUs before being processed to make pipelining more effective.

  source

  • LH0ezVT@sh.itjust.works ⁨2⁩ ⁨months⁩ ago

    This is the correct answer. Modern x86 (x64) is a RISC CPU with a decoder that can decode a cisc isa.

    source
  • Mihies@programming.dev ⁨2⁩ ⁨months⁩ ago

    From what I remember one of problems with CISC is that it has variable length instructions and these are harder to predict since you have to analyze all instructions up to the current one wheres for RISC you exactly know where is each instruction in memory/cache.

    source

    • The_Decryptor@aussie.zone ⁨2⁩ ⁨months⁩ ago

      one of problems with CISC is that it has variable length instructions

      RISC systems also have variable length instructions, they’re just a bit stricter with the implementation that alleviates a lot of the issues (ARM instructions are always either 16-bits or 32-bits, while RISC-V is always a multiple of 16-bits and self-describing, similar to UTF-8)

      source

      • Mihies@programming.dev ⁨2⁩ ⁨months⁩ ago

        I was thinking about Apple’s M CPUs that have fixed length and they benefit out of it. It was explained on Anandtech years ago, here is a brief paragraph on the topic. Sadly Anandtech article(s) isn’t available anymore.

        Since this type of chip has a fixed instruction length, it becomes simple to load a large number of instructions and explore opportunities to execute operations in parallel. This is what’s called out-of-order execution, as explained by Anandtech in a highly technical analysis of the M1. Since complex CISC instructions can access memory before completing an operation, executing instructions in parallel becomes more difficult in contrast to the simpler RISC instructions.

        source

        • -> View More Comments
    • Eknz@lemmy.eknz.org ⁨2⁩ ⁨months⁩ ago

      This isn’t completely true. Even a basic instruction like ADD has multiple versions once decoded depending on the memory used. For example, if the memory being operated on is in RAM, then the ADD needs to be decoded to include a fetch operand before it can be used.

      source

      • Mihies@programming.dev ⁨2⁩ ⁨months⁩ ago

        Yes, but RISC knows the exact position of that instruction in cache and how many instructions fit the instructions cache or pipeline. Like you said, it doesn’t help with data cache.

        source

        • -> View More Comments
  • Kazumara@discuss.tchncs.de ⁨2⁩ ⁨months⁩ ago

    Yeah if you build a RISC processor directly you can just save the area needed for instruction decode.

    source
• Mwa@thelemmy.club ⁨2⁩ ⁨months⁩ ago

  alr thanks for the info

  source