QBertReynolds

@QBertReynolds@sh.itjust.works

• ⁨Comment⁩ on ⁨Windows Defender Anti-vitus Bypassed Using Direct Syscalls & XOR Encryption⁩ ⁨⁨18⁩ ⁨hours⁩ ago⁩:

  No argument there. It’s also why it’s done in ARM, 8080, SM83, z80, 6502, and basically every other assembly language. It’s only not done in RISC-V because you can fold 0 into any instruction as an operand, therefore eliminating the need to clear a register before an instruction.

  So why correct the person with a more narrow claim that makes it seem like xor being faster than loading zero is a rarity in CPU architectures? If I said “birds can fly”, and your response was “eagles can fly. Ftfy. Not all birds can fly”, it would be both true and utterly unhelpful.

• ⁨Comment⁩ on ⁨Windows Defender Anti-vitus Bypassed Using Direct Syscalls & XOR Encryption⁩ ⁨⁨2⁩ ⁨days⁩ ago⁩:

  I never made that claim, nor did the person you corrected.

• ⁨Comment⁩ on ⁨Windows Defender Anti-vitus Bypassed Using Direct Syscalls & XOR Encryption⁩ ⁨⁨2⁩ ⁨days⁩ ago⁩:

  There are a lot more architectures than just x86 that are capable of XORing a register with itself (ie. ARM and RISC-V), and if you took OP to mean the accumulation register specifically, pretty much all CPUs going back as far as I can think have had that functionality.

• ⁨Comment⁩ on ⁨Framework temporarily pausing some laptop sales in the US due to tariffs⁩ ⁨⁨1⁩ ⁨week⁩ ago⁩:

  They have no idea how much more the trade war will escalate between the purchase and the item getting imported. If their laptops take several months to ship and their margins are lower than the increase in tariffs after the sale was made, then they lose money on the sale.