Machinist@lemmy.world the higher I can get the frequency, the less ripple I’ll have to deal with.
Why not just use a low-pass filter to remove the switching frequency? Most regulator outputs are already buffered with a large capacitor to stabilize the voltage, so adding the inductor to form an LC circuit is not exactly adding much.
However, there’s nothing really stopping me from doing variable frequency.
Why make this harder? A constant frequency simplifies the analog design, because you can do the bandwidth analysis once when verifying stability. A feedback loop that is statically and dynamically stable at one frequency might entirely fall apart at another frequency, because the frequency response of the regulator itself or the load may interact with the regulator frequency.
combine 3 pwm signals into one per channel
cpu begins grinding cycles to reset the buffers to adjust everything to a new duty center.
I’m struggling to see how this 20 MHz ATTiny would have so much trouble regulating a DC output that it needs to resort to rather strange techniques.
I mainly have experience on the TI MSP430 and ATMega328p, but both those microcontrollers have a robust PWM feature set that includes fixed waveforms that trigger an output whenever a value in memory is equal to the waveform. Such a value could also be the result of the ADC, meaning that zero CPU involvement is needed to keep regulation. That the ADC and PWM peripherals can be clocked independently from the CPU means this can all be done in the background, so the CPU can just go to sleep.
If the ATTiny3224 doesn’t have such capabilities, you would want to figure out another way to do things in the hardware peripherals – or even getting a different chip – than do regulation in software.
xthexder@l.sw0.com 1 day ago
I tend to agree with litchralee, changing the duty cycle is usually how these things are done rather than having multiple voltages.
From a control perspective, it’s much easier to turn a digital signal on for 1/4 the time than it is to generate 1/4 the voltage for the full time. But that’s just for basic PWM. If you’re trying to boost the voltage up from your source though, the mechanism for getting a target voltage is a bit different, and relies on “charging up” an inductor and disconnecting it to spike the voltage. I found this reference that seems to have some good diagrams of how it works: analogcircuitdesign.com/boost-converter/
In a boost converter, duty cycle and frequency should be tuned to the inductor so that energy isn’t being wasted after the inductor reaches steady-state and starts acting like a short circuit.
I explained it poorly. The chip has an ADC that can operate in window mode. I. E. when my output voltage jitters high or low out of bound, I can use logic to very quickly effectively increase or decrease my duty cycle. (Actually substitute another pwm signal that is in pnase but with a larger or smaller duty)
5V square PWM from the ATtiny goes to a gate driver capable of several amps at 5V, that gate driver switches a pair of logic level MOSFETs, one of the MOSFETs switching the coil and the other acting as the recitfier. Topology is a synchronus inverting buckboost.
Changing the duty cycle then raises or lowers the voltage.
At the same time, via interrupt or event channel, the cpu starts calculating a new duty cycle and setting the timers. Interrupts may take 100 cycles. Whereas, pwm at 625kHz will have completed an additional three cycles before I can even start to modify the duty from the program.
None of this may matter. Static dumb resistive load, I could probably just about run my MOSFETs off a 555 and not even worry about feedback or regulation.
However, the idea is interesting to me. Quick response regulation with more precise regulation happening as the CPU catches up.
Seems like it would give you a flatter output.
I’ve found when I discover an interesting electronic or programming technique or problem, that usually means I don’t know the name. It’s usually something figured out decades ago and there are references and papers that explain it and consider angles that I didn’t know about.
xthexder@l.sw0.com 1 day ago
I see, yeah that seems like a decent design going through the interrupt. Since your load is static, the responsiveness of your IC interrupts shouldn’t matter too much, but if you were trying to drive a high bandwidth load, then it would start becoming an issue. 625kHz or even the effective 200kHz you have control over would be plenty accurate even for something like audio (which wouldn’t change faster than maybe 48kHz). You can size your output capacitor accordingly so that if you suddenly hook up a bigger load, the voltage drop is acceptable until the IC can catch up.