PWM resolution for switch mode power supplies.

Submitted ⁨⁨1⁩ ⁨day⁩ ago⁩ by ⁨Machinist@lemmy.world⁩ to ⁨askelectronics@discuss.tchncs.de⁩

So, I’m tinkering with the ATtiny 3224 and its PWM capabilities. I can get 256 bits of resolution per cycle at 78.125kHz.

If I drop to 32 bits, that gets me to 625kHz, as shown in the screenshot.

I’ve done some searching but I may not know the right term and I’m probably looking for a rule of thumb.

What sort of resolution do you need to regulate a DC/DC switch mode? (in this case a pure resistive load that doesn’t change)

I think it might be something like a factor for required percentage of change of switch ON time. Such as, you should generally be able to modify your duty cycle by increments of 5% or 0.5% or whatever for proper regulation.

Does this factor have a name?

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ignotum@lemmy.world ⁨1⁩ ⁨day⁩ ago
I hope you mean 256/32 increments and not actual bits? I haven’t heard of a microcontroller with a pwm resolution above 16 bits

Think it depends a lot, higher frequencies means smoother current flow, higher resolution means less fluctuations, but if you have enough output filtering you can get away with pretty much anything i think

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- Machinist@lemmy.world ⁨1⁩ ⁨day⁩ ago
  The period is divided up into 32 pieces, instead of a 256 bit width, if that makes sense. So, the frequency is 20mHz/32 = 625kHz. 0b100000 / 0x20.
  
  Yeah, and with the load I’ll run, it’s not real critical. I just figure there has to be a name for this sort of tuning. If I know what it’s called, I can read up on it.
  
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litchralee@sh.itjust.works ⁨1⁩ ⁨day⁩ ago
In the context of DC/DC converters, I don’t know if there’s a specific name for the regulation precision. But analogizing from op amp designs, I think a reasonable term would be “gain”. This is because the objective of the regulation mechanism is to apply a change which brings the output voltage back to some target.

If the output has moved away from the target by -10 mV, then the objective is to adjust the output by -10 mV. But this cannot happen in instantaneous time. The feedback loop delay necessarily means a small lag. But even after the lag, if there is insufficient gain, the output might only be able to move -2 mV per feedback cycle. So it would take 5 cycles to return to the target.

By adjusting the PWM frequency, you might be able to reduce the length of time for each feedback cycle, so doubling the frequency might mean you can now move -4 mV/cycle. But in exchange, there is less precision. So rather than -4 mV/cycle, it now might be -8 mV/cycle.

Doing this for two cycles means the output voltage is +6 mV. So the next cycle would try to correct with -8 mV, which brings the output to -2 mV. And so on.

A higher frequency with reduced precision has resulted in an output that will “wobble” more, but it will indeed converge faster toward the target, when dealing with larger deviations.

A circuit without load that is statically stable will maintain a target voltage indefinitely. Applying a static load to this circuit will cause a temporary deviation, a subsequent correction, and then it’ll maintain the target voltage indefinitely. But applying a dynamic load means this process is repeated over and over. That is to say, dynamic stability is a continual transient condition, and so the analysis is very much related to what happens in a step transition: how a regulator reacts when going from stable to perturbed.

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- xthexder@l.sw0.com ⁨1⁩ ⁨day⁩ ago
  I think in the context of a switching power supply, this is just called voltage ripple. Generally it’s measured as the amplitude and frequency of the noise relative to the target voltage.
  
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- Machinist@lemmy.world ⁨1⁩ ⁨day⁩ ago
  Gain bandwidth seems to be really analogous to what I’m trying to figure out. If I can’t find a version that is more digital/pwm specific: it will probably be easier for me to figure out what minimum resolution I need experimentally.
  
  I’m looking at a constant frequency, variable duty drive as that seems the simplest. Also, the higher I can get the frequency, the less ripple I’ll have to deal with. However, there’s nothing really stopping me from doing variable frequency.
  
  The timer I’m using is TCA. I haven’t tried it yet, but it allows buffered register changes. I.E. the registers where I’m setting my duty and period can be updated in sync with the waveform. So, in theory, I can vary my waveform frequency and duty cycle all over the place. I’ll actually be using two of these signals, the other will be for a mosfet in place of the rectifier diode. Dead spacing shouldn’t be any trouble.
  
  I may even be able to use the programmable logic to combine 3 pwm signals into one per channel. I will have the spare internal outputs available.
  
  I’m still kind of studying on this and probably need to draw a picture. Say you have 3 square waves that all have the same period. They are synchronized on the rising edge. 1st signal is 25% duty, second is 50%, and the third is 75%. Depending on what a comparator is reading, your logic selects which signal to output. 50% to maintain and the others to drop or raise the voltage.
  
  So, if your voltage goes out of bounds, high or low, within a single clock cycle your square wave can be adjusted by some amount (25% amounts are just an example.) At the same time, your cpu begins grinding cycles to reset the buffers to adjust everything to a new duty center.
  
  It would probably be a small amount of fast logic adjustment. At a guess, 10% or less.
  
  I apologize if this is confusing and will draw it, if needed.
  
  Any idea what that would be called?
  
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  - xthexder@l.sw0.com ⁨1⁩ ⁨day⁩ ago
    I tend to agree with litchralee, changing the duty cycle is usually how these things are done rather than having multiple voltages.
    
    From a control perspective, it’s much easier to turn a digital signal on for 1/4 the time than it is to generate 1/4 the voltage for the full time. But that’s just for basic PWM. If you’re trying to boost the voltage up from your source though, the mechanism for getting a target voltage is a bit different, and relies on “charging up” an inductor and disconnecting it to spike the voltage. I found this reference that seems to have some good diagrams of how it works: analogcircuitdesign.com/boost-converter/
    
    In a boost converter, duty cycle and frequency should be tuned to the inductor so that energy isn’t being wasted after the inductor reaches steady-state and starts acting like a short circuit.
    
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  - litchralee@sh.itjust.works ⁨1⁩ ⁨day⁩ ago
    
    the higher I can get the frequency, the less ripple I’ll have to deal with.
    
    Why not just use a low-pass filter to remove the switching frequency? Most regulator outputs are already buffered with a large capacitor to stabilize the voltage, so adding the inductor to form an LC circuit is not exactly adding much.
    
    However, there’s nothing really stopping me from doing variable frequency.
    
    Why make this harder? A constant frequency simplifies the analog design, because you can do the bandwidth analysis once when verifying stability. A feedback loop that is statically and dynamically stable at one frequency might entirely fall apart at another frequency, because the frequency response of the regulator itself or the load may interact with the regulator frequency.
    
    combine 3 pwm signals into one per channel
    
    cpu begins grinding cycles to reset the buffers to adjust everything to a new duty center.
    
    I’m struggling to see how this 20 MHz ATTiny would have so much trouble regulating a DC output that it needs to resort to rather strange techniques.
    
    I mainly have experience on the TI MSP430 and ATMega328p, but both those microcontrollers have a robust PWM feature set that includes fixed waveforms that trigger an output whenever a value in memory is equal to the waveform. Such a value could also be the result of the ADC, meaning that zero CPU involvement is needed to keep regulation. That the ADC and PWM peripherals can be clocked independently from the CPU means this can all be done in the background, so the CPU can just go to sleep.
    
    If the ATTiny3224 doesn’t have such capabilities, you would want to figure out another way to do things in the hardware peripherals – or even getting a different chip – than do regulation in software.
    
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