Marcelo

@Marcelo@discuss.tchncs.de

• ⁨Comment⁩ on ⁨Using LLMs to Facilitate Formal Verification of RTL⁩ ⁨⁨1⁩ ⁨year⁩ ago⁩:

  In the paper, RTL stands for Register Transfer Level, in the domain of digital circuit design -> en.wikipedia.org/wiki/Register-transfer_level

• ⁨Comment⁩ on ⁨Using LLMs to Facilitate Formal Verification of RTL⁩ ⁨⁨1⁩ ⁨year⁩ ago⁩:

  Sorry about that, I should have spelled out RTL as Register Transfer Level in the paper. But yeah given the references to Verilog and hardware design it can be deducted…