It’s wild to read this classic 1991 paper that basically put the numbers behind the RISC vs. CISC flame wars. The authors wanted to figure out which processor architecture was actually better by comparing a RISC champ (MIPS M/2000) against a CISC heavyweight (VAX 8700).

To make it a fair fight, they picked these two specifically because their internal hardware pipelines were shockingly similar, even though the VAX was a massive, expensive beast and the MIPS was a sleek custom chip. This way, they could mostly blame the architecture itself for any performance difference, not the manufacturing tech.

The TLDR is that RISC absolutely crushed it. On average, the VAX had to burn through 2.7 times more CPU cycles to get the same work done. The whole RISC strategy was trading fewer, complex instructions for way simpler, fast ones. Even though the MIPS machine needed more instructions to finish a task, its cycles per instruction (CPI) were so much lower that it won by a huge margin.

The paper shows that the more complex a VAX instruction was (higher VAX CPI), the more simple MIPS instructions were needed to replace it, but the trade-off was always a big net win for RISC.

So why was MIPS so much better? The authors point to a few key architectural wins. First, MIPS had way more registers (32 general-purpose + 16 for floating-point) compared to the VAX’s 15, which meant it didn’t have to access slow memory as often. Second, basic operations like conditional branches were way faster on MIPS (1-2 cycles) than on the VAX (5 cycles), which was a huge deal. The MIPS architecture was also just smarter about keeping the pipeline full by using things like delay slots, which is basically doing useful work in moments that would have otherwise been wasted cycles—something the VAX couldn’t do.

The authors admit their study isn’t perfect, and they point out that compiler quality could have skewed the results and they only used a handful of programs for testing. But still, looking back, this paper was basically a prophecy for why modern CPUs, even from Intel, have a RISC-style core under the hood. It laid out the fundamental math for why the RISC approach was the future.