Hi everyone. I asked a question here before about my senior design project where I was planning on creating a RISC-V cpu.
I started the project and currently using iverilog, vpp and GTKWave (can also add yosys here but not for now) for development. And I plan on using Vivado for final implementation and IP’s.
Is this a good way of doing things? Should I just use Vivado? I feel like my approach is easier and lets me focus on the logic.
WagnasT@piefed.world 19 hours ago
Hopefully someone with more experience has a better answer but I’d say use whatever gets you across the finish line. I had a lot of luck with simple logic designs just using verilog but as things got complex I leaned harder into gui stuff like multisim. Playing with all the tools will help you with job interviews later. Even if you don’t end up favoring a specific tool being able to say what you like and don’t like about the tools will go a long way.