I explained it poorly. The chip has an ADC that can operate in window mode. I. E. when my output voltage jitters high or low out of bound, I can use logic to very quickly effectively increase or decrease my duty cycle. (Actually substitute another pwm signal that is in pnase but with a larger or smaller duty)

5V square PWM from the ATtiny goes to a gate driver capable of several amps at 5V, that gate driver switches a pair of logic level MOSFETs, one of the MOSFETs switching the coil and the other acting as the recitfier. Topology is a synchronus inverting buckboost.

Changing the duty cycle then raises or lowers the voltage.

At the same time, via interrupt or event channel, the cpu starts calculating a new duty cycle and setting the timers. Interrupts may take 100 cycles. Whereas, pwm at 625kHz will have completed an additional three cycles before I can even start to modify the duty from the program.

None of this may matter. Static dumb resistive load, I could probably just about run my MOSFETs off a 555 and not even worry about feedback or regulation.

However, the idea is interesting to me. Quick response regulation with more precise regulation happening as the CPU catches up.

Seems like it would give you a flatter output.

I’ve found when I discover an interesting electronic or programming technique or problem, that usually means I don’t know the name. It’s usually something figured out decades ago and there are references and papers that explain it and consider angles that I didn’t know about.