Comment on Intel CPU Temperature Monitoring Driver For Linux Now Unmaintained After Layoffs
Eknz@lemmy.eknz.org 1 day agoThis isn’t completely true. Even a basic instruction like ADD has multiple versions once decoded depending on the memory used. For example, if the memory being operated on is in RAM, then the ADD needs to be decoded to include a fetch operand before it can be used.
Mihies@programming.dev 1 day ago
Yes, but RISC knows the exact position of that instruction in cache and how many instructions fit the instructions cache or pipeline. Like you said, it doesn’t help with data cache.
Eknz@lemmy.eknz.org 1 day ago
Are you sure there’s a significant difference in machine code between RISC and CISC after instructions are decoded?
The assembly in RISC is just an abstraction of the machine code, as it also is in CISC. If the underlying CPU has the same capabilities then it doesn’t really matter what the assembly looks like?
Of course, the underlying CPUs aren’t the same and that’s the real point of differentiation.
Mihies@programming.dev 21 hours ago
See my other reply