Comment on China’s push for chip independence continues with its first RISC-V server CPU

• qprimed@lemmy.ml ⁨2⁩ ⁨weeks⁩ ago

  CPI per CPI… RISC, but thats a trap of a question and you know it ;-)

  tons of variables in that question, but there should be more headroom in RISC designs and thats why, internally, most things are RISC-y.

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  • lumony@lemmings.world ⁨2⁩ ⁨weeks⁩ ago

    It’s not a trap.

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    • qprimed@lemmy.ml ⁨2⁩ ⁨weeks⁩ ago

      ok. my apologizes.

      there really are tons of things to consider with that question. RISC has historically allowed for faster clocking and fewer cycles per instruction, so thats a win. RISC also requires more instructions per useful operation and also blows up the binary size, so… :-(

      all things being equal (hahaha) RISC has more headroom and legroom for future improvements that dont complecate the silicon to extreme degrees. the vast majority of CISC designs are now pretty RISC-like at their cores, but the software interface remains CISC and, I think, complicates and limits variety and advancement.

      imho, a properly spec’d RISC processor and a carefully designed compiler, cycle for cycle, macro for macro and watt for watt outperforms a CISC design (even with a RISC-like core). major computing holy wars are been waged over this for decades.

      all I currently have access to are older studies that show mixed general purpose results on RISC vs CISC (performance, not power efficiency), but if I had to make a choice about what my future ideal processor would be, it would be RISC core and RISC instruction set architecture simply due to less complexity, more efficient use of wafer space and lower power requirements. then we start talking about massively parallel RISC in tiny spaces and, for many (but not all) workloads, thats a big win.

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