Comment on China’s push for chip independence continues with its first RISC-V server CPU

• morrowind@lemmy.ml ⁨3⁩ ⁨weeks⁩ ago

  What do you mean by that. RISC-V is open source but it doesn’t have “superpowers” that I know of?

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  • qprimed@lemmy.ml ⁨3⁩ ⁨weeks⁩ ago

    “reduced” is the super power. I would much rather put the smarts into the assembler/compiler/interpreter than the silicon. have been followed RISC since the 80’s and discovered that I am really a RISC guy living in CISC world. open arch is the world dominating cherry-on-top.

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    • stsquad@lemmy.ml ⁨3⁩ ⁨weeks⁩ ago

      That’s not really true. Yes avoiding complex instructions makes the front end easier to pipeline but there are lots of smarts in the backend to do prediction and scheduling to keep the execution units fed. The ISA might be free to use but no one is sharing their highly optimised server silicon architecture designs.

      RISC-V’s challenge is can they standardise the software ecosystem enough that things just work across a multitude of chip providers or does everything devolve into specialist distributions taking advantage of each manufacturers “special sauce” custom instructions.

      Gaining design wins over Arm’s microcontrollers for bespoke hardware was the easy bit. Replacing stuff in the server space is much harder and something that took Arm decades to make inroads into.

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      • qprimed@lemmy.ml ⁨3⁩ ⁨weeks⁩ ago

        great reply. I am not saying RISC is the panecea, what I am saying is that there are more options for workload optimization further up the stack and rebalancing of the intelligence from the silicon to the software is an advantage.

        some time ago most CISC core design become more RISC-y and, to indulge in some ISA snobbery, I just want to slash and burn the CISC presentation to the software layer. memory is cheap, bus bandwidth is insane - simplification on the ISA just seems like a hardware complexity win all around and I am willing to pay for that in compiler complexity that incorporates changes more easily than hardware or CISC microcode.

        RISC-V’s challenge is can they standardise the software ecosystem enough[…]

        agreed. this is why I say my wait may be coming to an end.

        personally, I think RISC is the more flexible design in almost every usecase. cycle for cycle, RISC hits the right buttons for me across the widest number of situations once we get above the “magic hardware” layer. willing to flog the CISC vs RiSC horse convo if you have recent information, and thanks for the response.

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    • masterspace@lemmy.ca ⁨3⁩ ⁨weeks⁩ ago

      Do you have any resources by any chance that explain the difference well?

      I’ve coded in assembly and understand instruction sets at a very rough level, but I’m not really familiar with specifically what differentiates RISC / ARM / x64, or why RISC’s reductions would be good / bad / what trade-offs come with them.

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      • qprimed@lemmy.ml ⁨3⁩ ⁨weeks⁩ ago

        between the 30k’ overview of Reduced instruction set computer (RISC) architecture and the lower level RISC-V Architecture: A Comprehensive Guide to the Open-Source ISA, you should get a pretty decent feel for it.

        the level of optimization you get via hardware and software tooling is honestly pretty spectacular. I have been waiting for RISC to come out of hiding for years and it seems to be happening.

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    • Alphane_Moon@lemmy.world ⁨3⁩ ⁨weeks⁩ ago

      This is a purely theoretical arguement.

      Ecosystem momentum makes this argument mute.

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      • qprimed@lemmy.ml ⁨3⁩ ⁨weeks⁩ ago

        meh (not dismissive - just cute), ecosystem mootness is overrated. at the heart of every CISC beats a RISC. strip away the mask and lets poke the nuclear core.

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    • lumony@lemmings.world ⁨3⁩ ⁨weeks⁩ ago

      Which is faster?

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      • qprimed@lemmy.ml ⁨3⁩ ⁨weeks⁩ ago

        CPI per CPI… RISC, but thats a trap of a question and you know it ;-)

        tons of variables in that question, but there should be more headroom in RISC designs and thats why, internally, most things are RISC-y.

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  • fmstrat@lemmy.nowsci.com ⁨3⁩ ⁨weeks⁩ ago

    Image

    @SecondaryAnnetagonist@lemmy.blahaj.zone @Atomicbunnies@lemmy.dbzer0.com

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    • Atomicbunnies@lemmy.dbzer0.com ⁨3⁩ ⁨weeks⁩ ago

      Love it!

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  • InverseParallax@lemmy.world ⁨3⁩ ⁨weeks⁩ ago

    It’ll get there quick.

    I worked on HPC cpus, scaling up isn’t that hard, the hard part is dealing with your Isa baggage.

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• SecondaryAnnetagonist@lemmy.blahaj.zone ⁨3⁩ ⁨weeks⁩ ago

  Yeah, RISC is good.

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  • Atomicbunnies@lemmy.dbzer0.com ⁨3⁩ ⁨weeks⁩ ago

    Double the speed of a Pentium…

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  • fmstrat@lemmy.nowsci.com ⁨3⁩ ⁨weeks⁩ ago

    Wow, all the down votes. Youngin’s don’t know what they’re missing. Classic film.

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