nanometer is a marketing term now and doesn’t reflect actual sizes. Samsung were first with “3nm”.
America was doing “3nm” in 2018. You don’t seem to have any understanding of this issue.
From Wikipedia:
The term “3 nanometer” has no direct relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers.
Also from Wikipedia:
South Korean chipmaker Samsung started shipping its 3 nm gate all around (GAA) process, named 3GAA, in mid-2022. On 29 December 2022, Taiwanese chip manufacturer TSMC announced that volume production using its 3 nm semiconductor node termed N3 is under way with good yields.
In early 2018, IMEC (Interuniversity Microelectronics Centre) and Cadence stated they had taped out 3 nm test chips, using extreme ultraviolet lithography (EUV) and 193 nm immersion lithography.
kbotc@lemmy.world 8 months ago
The actual research that you’re giving Taiwan credit for is US research. There’s a reason the US was able to tell the Dutch government “You can’t allow this hardware to go to China.”
The basic research for the Extreme Ultraviolet lithography was done at US DOE labs as a hedge against Japan dominating the world semiconductor supply. The US allowed a few companies in as part of the EUV-LLC private-public partnership, and ASML ended up buying out the other players who had the licenses from the US. The EU certainly had a hand in the research after the test bed was built proving it could work. www.sandia.gov/media/ultra.htm