I am not 100% sure, but I think that the designer bears the cost of the wafer yield.

The PDK is specific to the manufacturer, and I imagine that the risk associated with specific features is known and the yield range can be estimated. A design with more and riskier the features would lower the expected yield, and it makes sense that this risk gets passed onto the designer. The contract may have some protections for the case when the yield is significantly lower than expected because of the manufacturer’s fault. Just a guess though, it would be great if someone with real experience can answer.