I think you should look in to MIPI from a hardware protocol perspective before committing to that route. The issue isn’t the physical connector, but the complexity of the protocol. I found some open MIPI cores. idk if you’re allowed to use open cores, but if they fit in your FPGA (with whatever other logic you need for your CPU and glue logic), then that may work, but if I were a student I’d probably be looking for a simpler interface where I can have the FPGA control the flow of data (like request 1 row of pixels at a time given the memory constraints).