That’s three devices. There’s two connections between them, and they go “RAM<->CPU<->SSD”. The first <-> is the DRAM Phy, the second <-> is 1-4 PCIe lanes. Neither of them are a bus. There is no third connection.
That’s three devices. There’s two connections between them, and they go “RAM<->CPU<->SSD”. The first <-> is the DRAM Phy, the second <-> is 1-4 PCIe lanes. Neither of them are a bus. There is no third connection.